senior DFT Engineer

DFT Test Engineer
Work location: Shanghai, Beijing
ASIC Product Development Group in GlobalFoundries is Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group consists of technology development, EDA/methodology development and IP/Chip design development. China DFT team is a key part of Global DFT community with global ownership and responsible for delivering DFT architecture, methodology and design. You will be working with this team to directly enable customer requirements for ASIC product development group.
 
Responsibilities:
Candidate will be responsible to implement DFT/Test on IP/SoC design as well as enable methodology for DFT Synthesis, verification and pattern generation. Candidate will work with worldwide design teams and research teams to influence the DFT/Test roadmap.
 
Requirements:
·       Masters of Technology
·       2-8 years’ experience
·       Mentor Graphic Toolset candidates are preferred
·       This position is required in the team which is responsible for delivering DFT / Test IP, Methodologies and Design for ASIC designs. Candidate need to be able to understand DFT/Test architecture. Candidate need to have hands-on experience in implementing DFT/Test in designs in the area of DFT Synthesis, verification and pattern generation/simulation. Additionally, Candidate need to be well versed with the design methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Testars experience
·       Strong knowledge in ASIC front end flows including Logic Design, Synthesis, DFT and STA. Strong fundamentals in Digital Circuit Design is required. Prior experience in ASIC design is a plus.  Scripting skills using PERL, Tcl and C-Shell.