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美满电子招聘

Campus Recruitment - Physical Design Engineer

收藏职位
  • 我要分享
  • 20万-25万/年
  • 上海
  • |
  • 应届生/在校生
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,股票期权,技术领先,成长空间大

发布时间: 2018-11-27发布

职位描述

Description:
-IC design implementation from RTL to netlist including synthesis, timing constraint composing, timing ECO, design for test
-IC physical implementation from netlist to GDSII, including floorplanning, power grid implementation, place and route, clock tree synthesis, timing ECO, design closure
-IC design verification including timing analysis, timing signoff, formal verification and low power verification.
-IC physical verification including physical verification, crosstalk analysis, power analysis, ESD analysis, EM analysis.
-Program development in TCL or Perl to improve productivity.
-You will have the opportunity to develop 16nm/12nm/7nm IC implementation flow for the most advance technology.
-As a member of central IC design team, you will play an important role to assist multiple Marvell’s business unit with challenge of different physical design jobs.

Qualification:
-BS/MS in ME, EE or CS. 
-Some experience and knowledge on process, parameters, synthesis, timing analysis, placement, routing, CTS, SI, power calculation, custom layout, timing analysis, DRC/LVS.
-Familiar with Verilog HDL, Spice;
-Programming-minded, expert on using Makefile/Tcl/Perl to improve efficiency and streamline process;
-Can Support complex physical verification, power signoff, flip-chip and physical implementation of large scale design with advanced low power feature independently. Support the flow development of new technology, methodology.
-Positive, active, self-motivated team worker, good verbal and written skills in English;
-DFT, synthesis, formal related experiences is a good plus;
-Experiences on Cadence, Synopsys, Mentor and etc. EDA tools is a good plus.

 

职位发布者

Marvell

7天

简历处理用时

97%

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