Campus Recruitment - Physical Design Engineer
-IC design implementation from RTL to netlist including synthesis, timing constraint composing, timing ECO, design for test
-IC physical implementation from netlist to GDSII, including floorplanning, power grid implementation, place and route, clock tree synthesis, timing ECO, design closure
-IC design verification including timing analysis, timing signoff, formal verification and low power verification.
-IC physical verification including physical verification, crosstalk analysis, power analysis, ESD analysis, EM analysis.
-Program development in TCL or Perl to improve productivity.
-You will have the opportunity to develop 16nm/12nm/7nm IC implementation flow for the most advance technology.
-As a member of central IC design team, you will play an important role to assist multiple Marvell’s business unit with challenge of different physical design jobs.
-BS/MS in ME, EE or CS.
-Some experience and knowledge on process, parameters, synthesis, timing analysis, placement, routing, CTS, SI, power calculation, custom layout, timing analysis, DRC/LVS.
-Familiar with Verilog HDL, Spice;
-Programming-minded, expert on using Makefile/Tcl/Perl to improve efficiency and streamline process;
-Can Support complex physical verification, power signoff, flip-chip and physical implementation of large scale design with advanced low power feature independently. Support the flow development of new technology, methodology.
-Positive, active, self-motivated team worker, good verbal and written skills in English;
-DFT, synthesis, formal related experiences is a good plus;
-Experiences on Cadence, Synopsys, Mentor and etc. EDA tools is a good plus.