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NVIDIA

IC功耗工程师 ASIC Power Engineer

收藏职位
  • 我要分享
  • 20万-40万/年
  • 上海
  • |
  • 工作经验不限
  • |
  • 本科
  • |
  • 全职

职位诱惑: 成长空间大,技术领先,福利好,免费班车

发布时间: 2018-11-29发布

职位描述

Shanghai power team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies for power optimization. We want to hire promising talent who can handle project(s) individually/collectively and also add new dimension to the team.
 
Responsibilities:

  • Create a methodology/algorithm to evaluate power efficiency on high-level (architecture) designs.
  • Support IP designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch (ASIC) level.
  • Understand and perform block level and chip-level power analysis.
  • Communicate/Cooperate with local and abroad teams with power-related projects.
  • Co-work with power ARCH team/IP team to evaluate new low-power technologies and improve chip power efficiency.
 
Requirements:
  • MSEE/MSCS postgraduate.
  • Experience in ASIC design/verification, low power knowledge is a strong plus.
  • Must be familiar with at least one of the programming languages, C/C++ (preferred), Python, Perl.
  • Excellent English writing/speaking skills are desired.
  • Good communication skills.

职位发布者

Heather

HR

7天

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97%

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