IC功耗工程师 ASIC Power Engineer
Shanghai power team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies for power optimization. We want to hire promising talent who can handle project(s) individually/collectively and also add new dimension to the team.
- Create a methodology/algorithm to evaluate power efficiency on high-level (architecture) designs.
- Support IP designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch (ASIC) level.
- Understand and perform block level and chip-level power analysis.
- Communicate/Cooperate with local and abroad teams with power-related projects.
- Co-work with power ARCH team/IP team to evaluate new low-power technologies and improve chip power efficiency.
- MSEE/MSCS postgraduate.
- Experience in ASIC design/verification, low power knowledge is a strong plus.
- Must be familiar with at least one of the programming languages, C/C++ (preferred), Python, Perl.
- Excellent English writing/speaking skills are desired.
- Good communication skills.