芯片功耗工程师 ASIC Power Engineer
1. Create a methodology/algorithm to evaluate power efficiency on high-level (architecture) designs.
2. Support IP designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch (ASIC) level.
3. Understand and perform block level and chip-level power analysis.
4. Communicate/Cooperate with local and abroad teams with power-related projects.
5. Co-work with power ARCH team/IP team to evaluate new low-power technologies and improve chip power efficiency.
1. MSEE/MSCS postgraduate.
2. Experience in ASIC design/verification, low power knowledge is a strong plus.
3. Must be familiar with at least one of the programming languages, C/C++ (preferred), Python, Perl.
4. Excellent English writing/speaking skills are desired.
5. Good communication skills.