ASIC Design Intern

4万-5万/年
上海
|
应届生/在校生
|
本科
|
实习

职位诱惑: 老板nice,免费班车,成长空间大

发布时间: 2019-03-14发布

职位描述

·        The candidate is preferred to be MSEE(CS or EE)
·           Understanding basic ASIC design flow
·           Sufficient knowledge in Perl/Python/Ruby/Java/C/C++ is a strong plus
·           With experience on Verilog or SystemVerilog
·           Nice to have development experience under Linux, knowledge of Shell/Make/VIM/…