IP Design-PCIE

Responsibility:
·       Responsible for Bus system design implementation and participate in the architecture level discussion and decision making.
·       Working with the Front-end team and PD team closely on the ASIC implementation flow for the SOC bus System or IP sub-systems.
·       Working with Verification engineer closely on functional and performance verification.
·       Supporting integration and qualification of SOC integration.
 
Requirement:
·       Familiar with AXI is a must.
·       Strong Verilog RTL coding capability is a must.
·       Hand-on experience in all domains of complex ASIC Implementation flow.
·       Good understanding of the verification, experience in verification work is a strong asset.
·       Familiar with scripting languages like Perl/Makefile…
·       Strong problem solving and communication skills
·       Knowledge on PCIE system is highly preferred.