Lead Design Engineer - STA

Position Description:
1. In charge of DDR IP logic design Implementation.
2. Daily duties include: RTL coding, Logic Synthesis, Static Timing Analysis.
3. HDL language Knowledge, like verilog or vhdl is necessary.
4. C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
5. Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics.
6. Excellent communication skills and the uncanny ability in a cooperative team environment are required.
7. Self-motivated, result-oriented, can take ownership and follow-through on tasks.
  
Position Requirements:
Essential Qualifications:
1. Master degree with 4~7 years’ experience
2. Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology or equivalent
3. Ability to work effectively alone or as well as in the team.
4. Essential that the individual demonstrates strong communication, verbal and written
5. Requires good communication skills in English.
 
Desirable Qualifications:
1. Experience of DDR