Sr. Engineer/Staff Engineer of Verification
- 20万-40万/年
- 上海
- |
- 工作经验不限
- |
- 本科
- |
- 全职
职位诱惑: 五险一金,福利好,老板nice,股票期权,天天下午茶,技术领先,成长空间大
发布时间: 2019-08-28发布
职位描述
Responsibilities:
1. Understanding the expected functionality of designs.
2. Developing testing and regression plans.
3. Designing and developing verification environment.
4. Running RTL and gate-level simulations/regression.
5. Code/functional coverage development, analysis and closure.
Requirements:
1. Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
2. Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…).
3. Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
4. Scripting and automation skills (tcl, perl, makefile etc) a plus.
5. Familiar with C/C++.
6. Knowledge of DDR/Video/ARM/USB/PCIE , Low Power Verification with UPF and design experience is a plus.
7. Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment. and Knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
8. Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
9. Independent and self-managing.
职位发布者
芯原微
HR
简历处理用时
简历及时处理率
芯原微电子(上海)股份有限公司
领域: 移动手持,消费电子,智能硬件
规模: 500-1000人
主页: http://www.verisilicon.com
工作地址:
2号线张江高科地铁站附近
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