Sr. Engineer/Staff Engineer of Verification

Responsibilities: 
1. Understanding the expected functionality of designs.
2. Developing testing and regression plans.
3. Designing and developing verification environment.
4. Running RTL and gate-level simulations/regression.
5. Code/functional coverage development, analysis and closure.
 
Requirements: 
1. Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
2. Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…).
3. Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
4. Scripting and automation skills (tcl, perl, makefile etc) a plus.
5. Familiar with C/C++.
6. Knowledge of DDR/Video/ARM/USB/PCIE , Low Power Verification with UPF and design experience is a plus.
7. Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment. and Knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
8. Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
9. Independent and self-managing.