Lead Liberate Application Engineer

Position Description: 
1.      To provide key technical support for library characterization product evaluations/benchmarks and to drive the customer engagement process to deliver Cadence solutions by working both independently and collaboratively when required.
2.      The applicant will be solving complex technical issues which deal with timing/Noise/Variation characterization for a myriad of circuits including memory designs and mixed signal design.
3.      To assist Customers to successfully adopt and deploy Cadence products and methodologies. The AE will implement Design and conduct performance experiments, automate analysis of performance/accuracy data and design/implement/facilitate optimizations as appropriate.
4.      The AE will work closely with Sales Management to identify sales opportunities, prioritize them and help develop winning sales strategies. Develop an understanding of the customer's needs and also of the competition's technology and sales strategies to create solutions that best meet our customer needs. Communicate customer requirements and feedback to Cadence Engineering groups and Marketing for issue resolution and to improved product features and quality.
5.      Conduct technical presentations, technical training, and product demonstrations to customers, including development of customized presentations as required.
 
Position Requirements:
1.      MSEE or BSEE plus 3+ years’ experience in Library characterization with knowledge of Tcl, Shell Scripting (sh, csh, AWK etc.) and excellent communication skills. Detailed knowledge of Liberty ™ Library data formats (NLM, CCS and ECSM) and transistor level (spice) simulation is required for this position. Written and oral fluency in both Mandarin and English are required Ability to travel within China for frequent onsite customer visits is a must.
2.      We prefer candidates with experience in:
·        Transistor circuit simulation and analysis using Spectre, Finesim, and/or Hspice
·        Static timing, signal integrity and power analysis tools (Cadence's Tempus/Voltus and Synopsys' PrimeTime/PT-PX)
·        Standard cell and IO/IP characterization and validation
·        Statistical variation simulation and modeling (Monte Carlo analysis) including LVF and AOCV
·        Creating or maintaining production characterization or QA/validation flows
·        Memory simulation and analysis using Spectre_XPS, Finesim_Pro and/or XA
·        Mixed signal design with knowledge of Virtuoso ADE
·        Design and simulation of large mixed signal blocks such as PLL, SERDES, DAC, ADC.
·        Memory design and characterization
3.      Good communication in English and good work attitude.