MTS Design Verification Engineer for Graphics IP

Responsibilities:
·       IP/block Spec / testplan documentation.
·       IP/block level test environment / test-bench setup.
·       Test case write and debug in IP/block levels for develop function, coverage and performance.
·       Work closely with SW team for development.
·       Work closely with FPGA/synstem engineering for pre-silicon or post-silicon debug/test if needed.
 
Requirements:
·       A minimum of M.S. in Computer Science, EE or equivalent.
·       5+ years working experience in Graphics IP design or verification.
·       Multiple projects experience on High Speed IC design.
·       Strong skill on Verilong & C++/UVM, and strong problem-solving skills.
·       Good communication skills on Mandarin and English, and good teamwork.
·       Would be a plus if having other IP developing experience.