DFT Engineer

·       Participate in SOC DFT specification and test concept
·       参与SOC DFT架构设计
·       Implement DFT features including SCAN, JTAG/Boundary SCAN, MBIST, Analog Macro test logic
·       负责逻辑综合并插入DFT逻辑
·       Generate DFT related timing constraints and work with backend team for timing closure
·       编写和DFT逻辑相关的时序约束，和后端工程师合作实现时序收敛
·       Generate and verify DFT structural patterns and functional patterns
·       生成用于量产的测试向量
·       Support test engineer debugging DFT patterns on ATE
·       协助测试工程师调试测试向量
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REQUIREMENTS:
·       BS in EE & CS.  MS preferred
·       电子类本科或硕士学历
·       Familiar with entire ASIC design flow
·       熟悉ASIC 设计流程
·       Experience with Cadence or other DFT tools or strong interests in DFT
·       有DFT相关经验优先
·       Should have strong analysis and problem solving skills
·       良好分析问题解决问题的能力
·       Must work well in a team environment
·       团队合作精神
·       Good communication skills
·       良好的沟通技巧