- 12万-24万/年
- 成都
- |
- 工作经验不限
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,六险一金,年度体检,福利好,老板nice,股票期权,天天下午茶,技术领先,成长空间大,交通补助,节日礼物,技能培训
发布时间: 2019-06-11发布
职位描述
Responsibilities:
- Develop environments for ZSP system functional verification.
- Write verification plans for ZSP system level IPs and systems.
- Develop verification environments for IP and systems using C, verilog, Assembly, SystemVerilog, etc.
- Contribute improvements to verification methodologies, and toolsets.
- Develop script for verification flow with Python, Perl, etc.
Requirements
- 3-8 years working experience. BS/MS/PhD in Electrical/Computer Engineering.
- Strong coding skills - using languages: Verilog, SystemVerilog, Perl, assembly, C++, C, Linux.
- Great debugging and problem isolation skills.
- AXI, AHB interconnect.
- Computer architecture, memory subsystems.
- Implementing verification methodologies including constrained random verification, coverage closure, Assertion Based Verification, Universal Verification Methodology.
- Background knowledge for DSP, CPU, Cache is better.
职位发布者
胡馨予
HR
7天
简历处理用时
100%
简历及时处理率
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