STA Engineer

15万-30万/年
上海
|
应届生/在校生
|
本科
|
全职

职位诱惑: 五险一金,福利好,老板nice,技术领先,成长空间大

发布时间: 2022-09-05发布

职位描述

Responsibilities：
The candidate will work with RTL designers and backend engineers to create/review timing constraints, analyze timing, generate timing ECOs to close design timing.

Requirements：
1. BS or above in EE, CS
2. Good understanding of advanced timing methodology concepts like noise, cross-talk, Advanced OCV, statistical STA, multi-voltage domain timing etc.
3. Understand the impact of improving placement, routing, cell sizing, buffering, logic optimization, etc. to design timing
4. Independent work experience on multiple million gates SoC timing sign-off.
5. Familiar with scripting language, such as, Perl, Python, Tcl, Shell.
6. Experience of synthesis/LEC and flow build up.
7. Working knowledge of Verilog.
8. Good verbal and written communication skills.
9. Ability to work in a team environment.
10. Organized and motivated.