FPGA/ASIC Frontend Design Engineering

Skills：
1. Good written and verbal communication skills.
2. Good programming skills in C/C++ and Verilog/SystemVerilog.
3. Good command of algorithms and data structures,  synchronous digital design principles and parallel computer architecture.
4. Good experience with standard industry EDA tools such as Vivado / Synopsys / Cadence.
5. Experience with any of the AXI/DDR/PCIe/Ethernet/RDMA/ONFI/Toggle bus protocols a plus.
6. Knowledge in any of the channel coding, machine/deep learning, database algorithms a plus.
7. Quick learning and self-motivated.
8. Good team player and willing to work under pressure.


Responsibility：
Junior (3 Year +) ：
1. Communicate and understand module level specification.
2. Write module level design document according to design specification .
3. Use RTL/HLS/OpenCL design flow (as appropriate) for module level development.
4. Write module-level testbench as unit tests and perform functional verfication.
5. Design space exploration and design optimization.
6. Board level tests.
Senior  (5 Year+)：
1. Same as Junior.
2. Independent project management executing the full cycle of project development.
3. Architecture design and specification, design, and test plan documentation.