数字后端设计工程师

职责描述：
1. Design automation; Construct, Guide, Modify, Enhance Timing tools and flows.
2. Responsible for full chip implementation from netlist to GDSII including floorplaning, place and route, power analysis, crosstalk analysis, timing and physical sign off .
3. Help develop the Backend Design flow 

任职要求：
Education Major: BSEE/CE or MSEE/CE 
Experience & Skill: 5 Years 
1. 3- 5 year of PR related work experience
2. Familiar with physical design tools and flow.
3. Successful tape-out experience is a strong plus. 
4. Analog/Mixed-signals design experience is a plus. 
5. Have DC/DFT experience is a plus.
6. Good programming skill (Python/Perl/Tcl) is a plus. 
7. Must be a good team player and have a good communication skills.