Intern for Power Convergence

Job description:
1. As Intern in SOC power convergence, the candidate will be responsible for Invention, research and development of power measurement and optimization solutions for GPU SOC.
2. The role should understand power management, clock solutions, analyze and optimization perf/power consumption for soul use cases, working with cross-function teams like Architecture/IP/FE/PV/Physical design team.

Job Requirement:
1. MS/PHD Candidate.
2. Knowledge of one of the domains below is prefer:
3. Knowledge of power management, performance (BW/Throughput/latency) definition.
4. Understand perf/power of ICs
5. Familiar with deep learning frameworks like TensorFlow, PyTorch, etc
6. Understand OpenCL, assembly code, C, Verilog/VHDL, UVM/OVM.
7. Scripting language (Python, Perl ) knowledge and UNIX/Linux experience is required
8. Experience in Design/Verification/debugging low power technologies like clock gating, power     gating, DVFS, stand mode, di/dt and so on…
9. Knowledge of the physic design and Design compiler.
10. Knowledge of GPU computing and basic understanding of Machine/Deep Learning is a plus.
11. Strong analytical skill and English ability, good at communicate and team work.
12. At least 3~4 days a week, 6 months.