- 26万-50万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,股票期权,天天下午茶,年度旅游,交通补助,技能培训
发布时间: 2020-02-11发布
职位描述
Responsibilities
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design；
2. Generating, simulation and debugging the test patterns for ATE manufacture testing；
3. Interface with back-end physical design team to complete timing closure for test related logic；
4. Interface with operation team to debug production test-vectors for wafer test and final test.
Requirements:
1. BS or MS, major in EE or related discipline;
2. 5+ years work experience in SOC DFT design;
3. Strong experience in ASIC logic design and verification;
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability;
5. Good communication capability and teamwork spirit.
更多地平线愿景可戳Bloomberg Markets: China Open 采访：https://mp.weixin.qq.com/s/4DtSP1rfqByShkuPQ0o_-g
职位发布者
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