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地平线机器人

Senior SYN/STA Engineer

收藏职位
  • 我要分享
  • 26万-50万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,股票期权,天天下午茶,年度旅游,交通补助,技能培训

发布时间: 2020-02-11发布

职位描述


Responsibilities:
1. Responsible for the RTL synthesis, SDC/UPF(CPF) analysis, Formal check, including:
ü   RTL synthesis for BLK and chip level;
ü   SDC analysis/check with FE engineer;
ü   Low power architecture analysis and check with UPF or CPF;
ü   Formal check for RTL to netlist and netlist to netlist of PR different stage;
ü   STA and timing fix with PR engineer for BLK or chip level timing closure;
ü    
Requirements:
1.>5 years of experience and minimum of BS in EE or equivalent; MS a plus. Experienced in one of the major SYN/STA/Lowpower tool suites (Cadence, Synopsys);
2. Experience with mainstream SOC architecture (ARM based, GPU, VPU, DDR …);
3. Scripting expertise (Perl, Tcl) a strong plus;
4. Actual complex SOC tapeout experience on a recent technology node (28nm or below) a strong plus.
更多地平线愿景可戳Bloomberg Markets: China Open 采访:https://mp.weixin.qq.com/s/4DtSP1rfqByShkuPQ0o_-g

职位发布者

李莉萍

HR

7天

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