As a key team member in Switching team, you will be responsible for:
- Implementing from Synthesis to GDSII out which including synthesis/DFT implement and check/P&R/ timing signoff and physical signoff
- Cooperate with colleagues on power fixing based on power analysis result
- Develop methodologies to make daily work more efficient
- Cooperate with designers on RTL issues which relative to BE timing closure and congestion solve.
- Debugging the flow issues in specified way.
- Proven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
- Experience with Synopsys /Cadence place-and-route tool set and physical design project implementation.
- Good programming skill. Capable of writing Tcl or Perl.
- Familiar with synthesis, static timing analysis.
- In-depth understanding of fabrication processing steps used in major fabrication industries.
- Self-motivated team worker, good verbal and written communication skills in English.