Digital Verification Engineer/Manager

Job Description:
In this key role, the candidate will be responsible for low power implementation and verification of acoustics hardware. Your primary scope of ownership includes verification planning, verification environment development, simulation, and data analysis.  You should also be comfortable contributing to ASIC design;
-Development of infrastructure for verification of hardware in Acoustics IP;
-Developing low power verification environments for feature test, and using the automated regression infrastructure setup for IP level and whole chip level functional verification;
-Low power design and verification for specific hardware functionality in front-end and backend;
The Area of main contributions:
-Plan, document, and implement ASIC verification strategy including determining appropriate toolset, methodologies, metrics, and coverage;
-Develop simulation platform and automate collection of verification metrics;
-Along with other designers, determine the appropriate course of action for correcting bugs found through the verification platform;
 
Candidate Requirements:
-BS, MS or PhD in Electrical Engineering or Computer Science;
-3+years of ASIC verification or low power design/verification experience;
-UPF based low power design/verification or acoustics knowledge are plus;
-Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level implementation till tapeout release;
-Should be familiar with the overall strategy of BT, IT and ST partitions;
-Advanced programming knowledge on Verilog/System Verilog, C/C++;
-Requires demonstrated technical expertise in the areas of low power design/verification methodology;
-Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.;
-Experience with expertise in developing testplans/testbenches, and writing/debugging test code/testbenches and working closely with the entire design team to ensure timely delivery and quality designs;
-Experience with advanced verification techniques such as formal and assertions a plus.
-Experience in silicon bring-up a plus.
-Should have excellent communication skills (both written and oral) and should be able to participate cross- functional engineering teams geographically;