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Cadence

Principal Design Engineer - FPGA

收藏职位
  • 我要分享
  • 40万-60万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,福利好,老板nice,年底双薪,股票期权,技术领先

发布时间: 2019-05-05发布

职位描述

Title: Principal Design Engineer

Job Description
Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.
 
Position Requirements:
The position requires BSEE, or equivalent, with a minimum of 5 yrs of industry experience in designing hardware systems.
Must have excellent communication skills, both written and verbal.
Technical expertise in FPGA design for either Altera or Xilinx products is required.
Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.
RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.
Verification using with Cadence simulation products is desired.
Experience with scripting languages like Perl, TCL C-shell is strongly recommended.
Experience with PCB tools is also desired.

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

95%

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