Lead Product Validation Engineer
- 35万-40万/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,老板nice,股票期权,技术领先,成长空间大
发布时间: 2019-07-22发布
职位描述
The Position Description is:
1. Carry timing correlation check between synthesis tool, P&R tool and signoff tool.
2. Proactively provide STA & delay Calculation development suggestions to R&D.
3. Build up STA & delayCal expertise and deliver support to field team and customers whenever needed.
4. Required to acquire expertise and ownership over existing product components as well as develop brand new product features.
The Position Requirements for T3 are:
1. Bachelor with 5 years related experience or Master with at least 2 years related experience in design house, FAB or EDA company;
2. Rich experience in IC digital flow (front-end or back-end);
3. Experience in advanced nodes designs or knowledge in timing closure is a strong plus.
4. Good Unix System knowledge and script skill of TCL/CSH/PERL.
5. Excellent capability of self-learning, problem solving skills;
6. Being proactive and self-motivated;
7. Good written English and oral English is a strong plus.
职位发布者
cadence hr
Sr.Manager&BP
简历处理用时
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海市 浦东新区 前滩世贸中心3期
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