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光梓信息科技(上海)有限公司

Analog & Mixed Signal Design Verification Engineer 模拟验证工程师

收藏职位
  • 我要分享
  • 21万-28万/年
  • 上海
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,老板nice,股票期权,成长空间大,年度旅游,技术领先,技能培训,福利好

发布时间: 2019-07-05发布

职位描述

职责描述:
1.    Run schematic and layout simulations using tools like Spectre, HSPICE, AFS;
2.    Perform analog simulations like noise analysis, loop stability, ac/dc/tran, monte-carlo analysis;
3.    Work with circuit design engineers and system architects to write test plans, present results, and communicate clearly with designers and project leader;
4.    Execute and develop verification workflows for design sign-off;

任职要求:
1.    Engineering degree in an electronic or microelectronic field and 2+ years working experience in integrated circuits design or verification.
2.    Understanding of basic analog building blocks and mixed signal blocks;
3.    Hands on experience in Cadence Virtuoso tools;
4.    Experience with behavioral modeling languages (Verilog, Verilog-A, Verilog-AMS, System Verilog) is a strong plus.
5.    Experience with scripting languages like Python, PERL, TCL is a plus.

其他:
1.    Good team player, attitude and thirst for continuous learning
2.    Strong communication and interpersonal skills
3.    Ability to function independently, be self-driven

职位发布者

Photonic HR

7天

简历处理用时

100%

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