数字电路设计工程师 Digital IC Design Engineer
For more information, visit www.dialog-semiconductor.com.
As part of our continued growth, we seek a Digital Design Engineer to support on all aspects of digital design and verification on next generation power management chips.
Working in CTC team based in Beijing / Tianjin, you will:
• Participate in IP and chip level architecture definition, derive functional and design specifications and analyse feasibility of technical and architectures.
• Implement design with Verilog to achieve specification goals. Simulate and debug the codes in the coding stage.
• Go through the frontend design flow to deliver qualified netlist. Co-work with back-end team to fix timing issue and check floor-plan.
• Write ASIC specific part of test plan. Prove functional correctness from block level to top-level.
• Design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, etc.)
• Support firmware/software bring-up and debugging.
• Work as the technical contact point on the ASIC area.
• Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
What we are looking for?
• 3+ years of experience with Master degree or 5+ years of experience with Bachelor degree.
• Strong RTL coding and familiar with front-end design flow
• Proven experience on synthesis, timing analysis and formal verification.
• Should be familiar with shell/perl/tcl programming in linux OS.
• Experience in mixed signal team is a plus, knowledge of analog design is a big plus.
• Experience in power management chip design is a plus.
• Experience in C/C++/SystemVerilog programming is a plus
• Good communication skills and fluent English.
IMPORTANT NOTE: The salary above is for REFERENCE ONLY; all salary numbers in our postings are subject to your seniority, experience, and technical expertise etc., and it’s NEGOTIABLE.