- Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR;
- Perform Full chip DRC/LVS/ANT/DFM/Timing Closure;
- Aotomate the design flow to promote efficienncy,improve RTL to GDS design flow;
- Participate in next generation physical design, methodology and flow development.
- BSEE with minimum 1+ year of P&R experience by using Innovus;
-Successful track records of taping out 28/16nm chips;
- Familiar with synthesis/STA flow is prefer;
- Be familiar with RTL to GDSII design flow;
- Be familiar with computer languages such as C, C++, Perl/Skill/TCL/C-shell;
- Self-motivated with good communication skills and team spirit.
Roger Tang 汤冯喆