关注微信 意见反馈

扫描关注摩尔人半导体招聘

摩尔人招聘
确定
查看帮助中心
对职位有兴趣?上传您的简历无需注册,即可直接投递您心仪的职位
NVIDIA

ASIC Engineer

收藏职位
  • 我要分享
  • 20万-40万/年
  • 上海
  • |
  • 应届生/在校生
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,年底双薪,股票期权,技术领先,成长空间大,交通补助,节日礼物,技能培训

发布时间: 2019-09-08发布

职位描述

欢迎直接登陆51job NVIDIA 2020校园招聘网申系统申请,谢谢

We have multiple directions for ASIC Engineer development, including IP design/verification, SOC design/verification, ASIC Physical Design, DFT Design, FPGA/Emu, etc.  We share them in a single JD 
What you’ll be doing: 

  • Micro architecture design. 
  • RTL (Verilog) coding. 
  • Design implementation using Synopsys/Cadence tools. 
  • Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction) 
  • Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off.  (PD Direction) 
  • Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction) 
  • FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction) 
  • Methodology in any of above areas. 
What we need to see: 
  • MS degree from EE/CS or related majors from a prestigious university. 
  • Good knowledge in digital circuit design. 
  • Experience in using Verilog HDL. 
  • Experience in various of ASIC EDA tools. 
  • Fluent in English reading and writing. 
  • Self-motivated, good team player. 
Ways to stand out from the crowd: 
  • Proven ability to work independently as well as in a multi-disciplinary group environment 
  • Good command of C/C++ programming language. 
  • Mastery in one of the below areas 
  • Video codec. 
  • Encryption/Decryption. 
  • Processor architecture. 
  • Signal/image processing. 
  • Pattern recognition/machine learning. 
  • Data science. 
  • System on Chip. 
  • Memory interface. 
  • Understand ASIC design flow, hands-on experience in using industrial standard EDA tools is a plus.
  • Basic DFT knowledge including Boundary Scan, 1500, MBIST, Scan, ATPG is a plus 
  • Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is a plus 
  • Proficient user of script language like Perl, Python or TCL is plus 
  • Experienced in FPGA/EMU related implementation is a plus 
  • Experienced in Linux PCIE driver or other SW works is a plus 
  • Experienced in SystemC or UVM or SV or SCE-MI or other standards is a plus 
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. 

职位发布者

sbai@nvidia.com

HR

6天

简历处理用时

74%

简历及时处理率

您还未登录。已有账号, 点此登录,直接投递

推荐朋友

一键投递