VLSI Physical Design CAD Engineer

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VLSI Physical Design CAD Engineer  
 
We are now looking for Physical Design CAD Engineers. 
What you’ll be doing: 

• Analysis on placement, routing, timing, clock, power, noise and DFM. 
• Responsible for flow automation, regression testing. 
• Work with EDA vendors on tools evaluation and improvement. 

• Develop inhouse tools and solutions. 

• MSEE in CS/EE/ME. 
• Basic knowledge of device model, processing technology, timing, noise and power in chip design. 
• Proficient user of Perl/TCL/C/Python is preferred. 

• Hands-on experiences in EDA software from Synopsys (DC/ICC2/STAR-RC/PT/ICV), Cadence (Genus/Innovus/Quantus/Tempus/PVS), ANSYS (Seahawk/Redhawk) etc is a plus. 
• Hands-on experience in DL/ML projects/programs is a plus. 

• 对芯片的布局、布线、时序、时钟树、功耗、信号完整性和可制造性设计指标进行分析。 
• 负责流程自动化以及回归测试。 
• 与自动设计工具提供商合作，进行工具评估和改进。 
• 开发内部工具和解决方案。 

• CS/EE/ME等专业的硕士学位。 
• 关于器件模型、半导体工艺、芯片时序功耗与信号完整性的基本知识。 
• 优先考虑能够熟练使用 Perl/TCL/C/Python的候选人。 

• 主流自动化设计工具（例如DC/ICC2/STAR-RC/PT/ICV，Genus/Innovus/Quantus/Tempus/PVS，或者Seahawk/Redhawk等等）的上手经验 
• 深度学习/机器学习项目的上手经验