Intern for physical design and power reductions

Job Responsibilities:
Mainly target is to work on below key areas for Power team:

• Power reduction Methodology in Digital physical design
• Floorplan, Place and Route , Timing/DRC/IR/EM checking/fixing
• flows/tools methodology

•  Understanding basic ASIC design flow

• Tier 1 or 2 University, institute

• Master student in microelectronics, or related area
•  With experience on Verilog or System Verilog
• Sufficient knowledge in Perl/Python/Ruby/Java/C/C++ is a strong plus
•  Nice to have development experience under Linux, knowledge of Shell/Make/VIM/…