Low Power Design Engineer

RESPONSIBILITIES:

• Understand the architecture of the graphics IP and functional block being designed
• Defining low power methodology & Driving Low power design cross multi-IP/SOC teams
• Debug function/performance/power bugs of graphics IP
• Develop power simulation flow for power analysis
• Deliver, check and analyze power report
• Work with global Front-End design team and physical design team for improving large scale ASIC chips performance/watt parameter.

• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
• Must have one hands-on experience of the following area: driving Low power design / defining low power methodology / Block or Chip level RTL Design / block or Chip level design verification.
• Some design implementation (from synthesis to P&R ) experience is a plus.
• Aspiration for low power design is required.
• Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime PX, Conformal LEC. Good knowledge of datapath compilers is required.
• Should be able to work closely with RTL Design team , design verification team and backend physical design teams across multiple sites.
• Must have good communication & Analytical thinking skills.
• Having proficiency in flow development and scripting(PERL, TCL, PYTHON, SHELL) is a strong plus.

• Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area