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AMD

SMTS IP Graphics Verification Engineer

收藏职位
  • 我要分享
  • 40万-65万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,技术领先,成长空间大,交通补助

发布时间: 2020-08-25发布

职位描述

Responsibility:
·        Understand the design spec
·        Develop test plan and write tests to verify DFT IP in IP level or SOC level
·        Work with RTL designers and others to debug the failed tests
·        Run verification related flows and fix issues
·        Complete the verification target at each milestone
Requirement: 
·        Master with 8+ (or Bachelor with 10+) years working experience in ASIC area
·        Solid experiences with simulation model creation and the testbench build
·        Excellent knowledge of design verification methodology, such as OVM/UVM, SystemVerilog
·        Advanced programming knowledge on C/C++, perl, Tcl/tk, Makefile
·        Familiar with Linux Environment
·        Candidate must have one or more of the following experience/knowledge: 1) Micro-processor (e.g. ARM) architecture and peripheral; 2) Popular on-chip bus (AMBA/AXI) or NOC; 3) low power design and verification methodology; 4) Standard IO IPs, including SPI/SMBUS/GPIO/I2C/I2S/UART; 5) DFT/JTAG, etc.
·        C/C++ software development experiences is a plus
·        Verilog programming skill is a plus
·        Good communication skill and fluent English
·        Good team player and strong sense of responsibility
·        Strong problem solving skills
 

职位发布者

vicky cai

HR

7天

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