SMTS IP Graphics DFT Engineer
- 40万-65万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,福利好,老板nice,交通补助
发布时间: 2020-05-12发布
职位描述
RESPONSIBILITIES:
- Implement GC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
- Perform verification on all DFT structures
- Generate DFT related timing constraints and work with PD team for timing closure
- Generate and verify DFT structural patterns and functional patterns
- Participate in ATE bring-up and debug the DFT patterns on ATE
- Design and implement other DFX (debug, characterization, yield etc) logics
REQUIREMENTS:
- Master degree in EE/CS with at least 9 years’ experience, or Bachelor degree with at least 12 years’ experience in IC or semiconductor industry
- Minimum 6 years of experience in DFx-related areas
- Hands on working experience on ASIC DFT design and verification, familiar with entire ASIC design flow
- Strong analytical/problem solving skills and pronounced attention to details.
- Must be a self-starter and able to independently drive tasks to completion.
- Strong interpersonal and communication skills