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Synopsys

Verification Application Engineer (VCS)

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  • 我要分享
  • 35万-45万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,老板nice,技能培训

发布时间: 2020-04-09发布

职位描述

Job Title: Verification Application Engineer (VCS)
Location:Shanghai

Description:
Verification is the number one bottleneck in SOC designs today. Synopsys is uniquely positioned to offer the most complete verification solution in market today. VCS is the Platform for Synopsys verification flow. It incorporates a suite of built-in high performance next generation technologies for test bench automation, assertion based verification, coverage closure, etc., which are needed for verifying challenging multi-million gate designs.
Verification AE’s have the opportunity to work with various customers, giving them abundant exposure to different design styles and verification methodologies that are being used in the industry today. To achieve first-pass silicon all the RTL code must be thoroughly and effectively verified. This requires advanced test generation, simulation, formal analysis, Verification IP, and comprehensive coverage technologies. He/She partners with customers helping them implement these technologies in their complex verification environments through training, deployment assistance, methodology guidance, and technical account management. This keeps the verification Ac abreast with the complex verification environments being used in the Semiconductor industry today.
The verification AE works with Synopsys Sales Team on product demonstrations, evaluations, and competitive benchmarking. He/She plays an active role in account planning and works as part of the account team to develop solutions to customer problems based on their insight into the customers' needs and issues. He/She is the face of Synopsys at the customer site and the eyes and ears for Synopsys at this account.
Requirements:
1. BS degree in CS/EE with 5+ years of experience as a verification engineer.
2. Experience in developing verification environments for complex ASICs using OpenVera/SpecmanE, SystemVerilog or SystemC/C++ is required
3. Experience with verification methodologies such as VMM, OVM or UVM is preferable
4. Understanding of standard bus protocols such as AMBA, USB and PCI-E is a plus
5. Excellent verbal and written communication skills
6. Excellent customer interface, negotiation, communication and planning skills

职位发布者

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HR

7天

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