Emulation senior engineer

ob Title
Emulation (Sr. Engineer/Engineer)
 
Job Overview             
We are seeking emulation engineers to verify the RISC-V based SOC emulation platform. Individuals in this team will be involved in all phases of developing the platform, from programming emulation test-plan, building up emulation platform, running test cases and debugging fail cases. In this team, individuals will work with design team to verify the SoC, including CPU core, coherent management, PCIe, DDR, Caches and coherence bus system. 
 
Location
Beijing/Shanghai
 
Minimum Qualifications
We are looking for individuals that have 3+ years’ experience or equivalent education in the following areas:
1.     Develop emulation infrastructure for testing RISC-V based SOC.
2.     Bring-up independent portions of the SOC with self-checking tests.
3.     Bring-up CPU core and inter-connected IPs.
4.     Bring-up all interfaces of the SOC by working with RTL, Firmware and Tool Vendors.
5.     Experience with Emulation (palladium, veloce or zebu).
6.     Deep understanding of CPU, Memory subsystems and interfacing with - peripheral hardware.
7.     Familiar with Verilog/C
 
Preferred Qualifications
Additional skills in the following areas are a plus:
1.     Knowledge in C++/TCL/Perl/System Verilog programming.
2.     Familiar with DDR/PCIE/GIC.
3.     Experience with coherence protocol implementation, such as ACE, CHI. 
4.     Understanding of Kernel and driver level software
5.     Knowledge of design and good communication skill with design team.
 
Education Requirements
Required:  MS or BS with 3+ years’ experience in ASIC/SoC emulation