GFX FE tile owner

RESPONSIBILITIES:
• Work with global FrontEnd design team and physical design team for large scale ASIC chip physical implementation
• Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
• Work with Physical Design team on Floorplan, budgeting, timing closure, signal integrity, ECO flows, Power analysis, etc.
• Resolve formality, leda, CDC, connectivity and repeater issue.
• Analyze gating efficiency report to improve RTL quality and optimize power.

REQUIREMENTS:
• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
• Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC..
• Some Physical Design exposure required.
• Some exposure to DFT is a strong plus.
• Expertise in script (Perl, Tcl) is a must.
• Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
• Must have good communication & Analytical thinking skills.

EDUCATION:
• Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area