IP Subsystem Design Engineer ( PCIe）

Job Title：IP Subsystem Design Engineer ( PCIe）
Location：Beijing
 
Descriptions：
Are you a creative, highly motivated individual with a passion for “doing it right”?
Do you thrive in an environment where delivering customer satisfaction “goes without saying”?
 
As a Subsystem engineer in the Solutions Group at Synopsys, you will be responsible for the successful integration and customization of IP Subsystems involving both digital controller and mixed signal physical layer IPs selected from our broad portfolio of interface IP. You will also work closely with Marketing and IP R&D teams to collaborate on IP customizations, integration, verification and implementation of IP Subsystems. You will analyze and resolve complex Subsystem usage/implementation issues and provide timely, accurate technical guidance to customers. You will also be responsible for contributing to the authoring of the associated Subsystem documentation such as user guides, application notes and white papers that promote the Subsystems' ease of use, or address specific challenges in its implementation. You will have regular contact with external customers and internal contacts across cross-functional teams. Occasional travel will be required.
 
 
Responsibilities
 
•Lead and/or assist with the planning, co-ordination and execution of functional specifications for complex IP Subsystems.
•Integrate digital controller and mixed signal physical layer IPs.
•Design customization features.
•Check design quality in LINT/CDC/RDC/DFT, synthesize design and do equivalence check.
•Debug design in simulation and emulation.
•Proactively engaging with customers during SoC integration and silicon debug.
 
Education and Experience
 
•Bachelors and/or Masters Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science.
•Minimum of 5 years relevant experience in ASIC/SoC design or implementation.
•Full understanding of digital design methodologies and tools including RTL coding in Verilog, simulation, synthesis, static timing analysis, and formal verification.
•Domain knowledge of one or more of the following protocols:
-         DDR - DDR3, DDR4, LPDDRR3, LPDDR4
-         PCI Express – Gen2, Gen3, Gen4
-         USB – 2.0, 3.0, 3.1
 
•Must have experienced at least one ASIC/SoC tape-out from concept to full production.
•Experience with silicon bring-up and silicon debug activities.
•Technically creative, results oriented with the ability to manage multiple tasks efficiently including customer support issues and priorities.
•Strong communication skills and ability to interact with customers as well as peers.
•Adaptability to fast moving, changing environment with constant challenge.
•High degree of self-motivation and personal responsibility.
•Have the ability to work well within a team environment.