DDR Product Development Eng

What you do at AMD changes everything
At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

DDR Product Development Eng
 THE ROLE:
Processor silicon DDR interface electrical test and debug engineer.  In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & test plans, & debugs electrical issues in the memory sub-system of new processors. The job entails extensive hands-on lab work as well as technical leadership and communication across teams.
 
THE PERSON:
Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR3/4, LPDDR4/5 Memory test experience on electronic components such as uProcessors would be considered a big plus.
 
KEY RESPONSIBILITIES:
·       Provides DDR technical leadership in the development of new test & validation features
·       Closely interacts with silicon design (DRAM controller and phy) in test execution & debug, as well as in feature definition for future product generation
·       Writes comprehensive electrical & functional test plans for the memory validation of processors
·       Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers.
·       Debug of electrical & functional issues of the memory sub-system of new processors
·       Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.
·       Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug of the memory sub-system.
 
PREFERRED EXPERIENCE:
·       Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR3/4, LPDDR4/5 Memory test experience on electronic components such as uProcessors would be considered a big plus.  
·       Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
·       Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation
·        Requires good written and oral communication skills.  
·       Demonstrated ability to communicate with a variety of engineering disciplines and management.
·       Demonstrated experience with Python, Perl, Ruby language.

ACADEMIC CREDENTIALS:
BS-EE / BS-CE with directly related experience. An advanced degree will be considered a plus.