Foundation IP Design Engineer标准单元库设计工程师

esponsibilities:

1. Design and develop deep sub-micron foundation IP circuits including standard cells, memory and customization cells for chip PPA optimization
2. Guide layout designer, assist in layout optimization based on post-layout simulation results
3. Supervise junior engineer
4. Design implementation of digital block in Mixed Signal circuit, including synthesis, STA and simple verification
5. Design testchip for STD/MEM/IO libraries and assist in testing.

1. Minimum MS degree in EE or related majors with minimum five years experience
2. Hands on project experiences on circuit designs with strong background on device physics.
3. Familiar and hands-on experience in script language and behavior model, ie,Tcl, Perl, Verilog, etc. Familiar with Cadence/Synopsys/Mentor's EDA tools
4. Knowledge and experience on state-of-the-art semiconductor technology. Experience with low power design is a plus
5. Knowledge of digital design flow
6. Self motivated, good communication and team work skills are a must.