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芯原

ASIC Front-End Flow(综合/时序分析)-Engineer/Sr./Staff

收藏职位
  • 我要分享
  • 25万-50万/年
  • 上海
  • |
  • 工作经验不限
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,年底双薪,股票期权,天天下午茶,技术领先,成长空间大,交通补助,节日礼物,技能培训

发布时间: 2020-05-09发布

职位描述


Responsibilities:
1. Comprehend the SoC clock structure and working mode and prepare the SDC file for SoC design.
2. Prepare the DFT plan for the SoC design.
3. SCAN/MBIST/BSD insertion and synthesize methodology for Flatten/ Hierarchical design.
4. Pre/Post simulation for test patterns.
5. Cooperate with timing engineer for timing signoff (STA).
6. Analog IP test implementation and simulation.
7. Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure.
8. Formal check of RTL and netlist.
 
Requirements:
1. Bachelor's degree or above, major in EE, CS or relevant.
2. Above 5 years work experience to the one with Bachelor's degree and above 3 years with Master's degree is required for Senior Engineer position.
3. Skilled in SoC PPA, better for low power design.
4. Improve low test coverage to achieve higher coverage.
5. Skilled in csh/perl/tcl scripts.
6. Be familiar with concept of SoC and P&R physical implementation.
7. Fluent in both English and Chinese.
8. Good team work spirit
 

职位发布者

芯原微

HR

7天

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