IC设计工程师 ASIC Design Engineer (Clock)
Nvidia has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today.
The GPU clocks group is looking for an outstanding Senior ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team works with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team so it can design an efficient clock programming sequence. It also works the silicon solution team to triage silicon or programming bugs in the lab.
What you'll be doing:
- As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency clocks.
- You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints.
- Your understanding of System Verilog will be valuable to verify the clocks design.
- Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.
- Collaborate with Software and product design teams to debug GPU clock silicon bugs in our new products.
- BS or MS (preferred) in EE with 5 years of meaningful work experience.
- Your ability to thrive in a dynamically changing environment.
- Validated experience in RTL design (Verilog), verification and logic synthesis.
- Your strong coding skills in Perl or other industry-standard scripting languages.
- Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
- Experience in implementing on-chip clocking networks is desireable.