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Cadence

Principal / Lead Application Engineer

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  • 我要分享
  • 30万-50万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,股票期权,技术领先,成长空间大,交通补助

发布时间: 2020-04-23发布

职位描述


Position Description:

1.   Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
2.   Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
3.   Train, ramp-up and accompany customer project.
4.   Conduct basic and advanced trainings, presentations and demos as necessary.
5.   Providing technical expertise to address clients’ queries, which need expert involvement.
6.   Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
 
Position Requirements:  4-6 or above years’ experience in the following areas:

1.      Design experience in Verilog/VHDL for IP or SoC chip level.
2.      HW verification with knowledge of System Verilog/VHDL and HDL simulators
3.      Experience with hardware emulator or accelerator is a big advantage
4.      Advanced Verification Methodology like UVM is a plus
5.      Knowledge of Unix and Linux is highly desired
6.      Strong verbal and written communication skills in English
7.      Strong teamwork skills with good human relationship
 

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

97%

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Cadence

Cadence

领域: 移动手持,消费电子,通信网络

规模: 500-1000人

主页: http://www.cadence.com.cn/

工作地址:

上海市 浦东新区 前滩世贸中心3期

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