- 50万-70万/年
- 上海
- |
- 5年以上
- |
- 硕士
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,年底双薪,股票期权
发布时间: 2020-05-28发布
职位描述
Responsibility：
- As a DFT project leader, you should be work as a chip or sub-chip DFT leader for high performance ASIC design.
- Understand frond-end and back-end design requirement and limitation.
- Support Customer on advance DFT feature requirement.
- Specify the project DFT Design spec.
- Help Block level DFT engineer to resolve key design problem. Develop and maintain project DFT flow.
Requirement:
- 5 years+ DFT experiences and 2 year + top level DFT project experience.
- Deep understanding on DFT Design for large scale and high performance SOC chip design.
- Strong knowledge on STA and Test timing closure.
- 2+ Tapeout ATE bring-up and diagnose experience Massive product ASIC design experience.
- Solid Background on Verilog and SOC design
- Familiar with SNPS and Mentor DFT tools Familiar with PT or Tempus STA tools
- Familiar with simulation and ATE debug Good at makefile, tcl and perl scripts
职位发布者
Roger Tang 汤冯喆
Recruitment Expert
7天
简历处理用时
100%
简历及时处理率
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