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MPS

IC Layout Engineer 模拟IC版图设计工程师

收藏职位
  • 我要分享
  • 10万-20万/年
  • 成都
  • |
  • 应届生/在校生
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,福利好,老板nice,技术领先

发布时间: 2021-03-19发布

职位描述


In this position, you will work closely with circuit designers both in China and US to perform original, customized analog / mixed signal IC layout.该职位将紧密与中国区和美国区的IC设计工程师一起去完成新产品的,全定制的模拟和混合信号IC版图设计.
Responsibility岗位职责:
·         Main responsibility is analog / mixed signal IC layout主要负责模拟和混合信号IC版图设计
·         You will be responsible for all levels of analog mask layout from floor planning, ESD pad placement, block level layout up to top level integration and tape out主要负责所有模拟电路版图的整体布局、静电保护设计和模块到顶层的集成设计和流片
·         You will communicate and get directions from the analog design engineers to ensure high quality 主要负责与模拟IC设计工程师沟通并确定方向以确保产品的高质量
Requirement 岗位要求:
·         BS degree in electronics or microelectronics engineering or equivalent电子工程学或微电子学等专业,本科及同等学历
·         Understand the basic fundamental of electrical engineering具备基本的电子工程知识
·         Understanding of layout impact on device matching, noise coupling from signal, supply and substrate 知晓版图设计对器件匹配,信号干扰,信号线及衬底的影响
·         Understanding basic characteristics of transistor, resistor, capacitor and diode 具备基本的晶体管、电阻器、电容器和二极管知识
·         Understanding the importance of signal flow, power/ground structure and block placement in layout floor planning知晓信号走向,电源及地线结构和模块顶层布局的重要性
·         Understanding the importance of communication with analog designers知晓该工作与模拟电路设计师沟通的重要性
·         Must be familiar with DRC/LVS verification tools需熟悉DRC/LVS等验证工具
·         Must be familiar with Unix OS 需熟练操作Unix OS系统
·         Must be familiar with layout tools, such as Cadence Virtuoso, etc.需熟练操作Layout 工具,如:Cadence Virtuoso等
·         English, written and verbal, sufficient for technical discussions英语读写流利,能进行技术交流和沟通
 

职位发布者

MPS HR

7天

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100%

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