• Validate, debug, and understand PCIe link training (LTSSM), Data Link Layer (DLLP), and Transaction Layer (TLP).
• Plan, develop, and execute post-silicon validation plans
• System level debugging of post-silicon hardware and software issues
• Build and support validation infrastructure through the development of embedded software, device drivers, and test tools
• Bachelor or Master degree in CS, CE, EE with 7+ yrs.
• Knowledge of PCI/PCI Express system architecture.
• Excellent knowledge of PCIe link training (LTSSM), Data Link Layer (DLLP), and Transaction Layer (TLP).
• Experience with PCIe Analyzers / Exercisers.
• Proficient in Python/ C programming.
• Ability to develop functional validation plans and develop software necessary to execute these plans.
• Excellent knowledge of digital systems and computer architecture
• Experience developing device drivers for Windows or Linux
• Experience in use of lab equipment (e. g., protocol analyzers/exercisers)
• Excellent verbal and written communication skills