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澜起科技

设计验证工程师

收藏职位
  • 我要分享
  • 30万-45万/年
  • 西安
  • |
  • 3年以上
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 五险一金,年度旅游,技术领先,成长空间大,老板nice,福利好,十五薪,节日礼物,股票期权

发布时间: 2020-11-25发布

职位描述

JOB DESCRIPTION:
- Participate ASIC digital verification for various IP/SoC projects;
- Create verification plans with designers;
- Develop DV architecture and verification environment;
- Verification execution and sign-off;
SKILLS MANDATORY:
- Excellent team working style;
- Solid IP/SoC verification background:
- Mass production for verified IP/SoC
- Master with3> years working experiences on ASIC digital verification
- Familiar with DSP、CPU or Trace & Debug verification
- Production experiences on verification strategies and testplans;
- Familiar with SystemVerilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;
- Production experiences on ARM buses, such as AXI/AMBA/APB is a plus;
- Familiar with verification tools ;
- Familiar with Linux, csh/Python or any script languages;
- Good English skills (read and write).

职位发布者

Peter

HR

7天

简历处理用时

100%

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