FPGA Verification Engineer
- 21.6万-43.2万/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全职
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发布时间: 2020-08-24发布
职位描述
FPGA Verification Engineer
Location: Shanghai
Job Responsibilities
As a FPGA verification engineer, the candidate will be responsible for functional verification of networking FPGA with modern verification technology, such as UVM. Responsibility includes understanding functionality of the design, developing test plans and components of verification environment, running regressions, debugging failures and report design issues, measuring functional and code coverage and improving test cases to meet coverage goals. This candidate will work closely with FPGA design and DV team.
Job Qualifications
• Experienced in writing and debugging VMM/UVM-based verification environment and test cases;
• Familiar with coverage driven, constraint random based verification methodology;
• Familiar with function/code coverage and assertions;
• Familiar with EDA tools, such as VCS and DVE;
• Experience in developing automation scripts, such as Makefile/Python/Perl/Tcl/Shell is a plus;
• Experience of Synopsys’ DesignWare VIP for Ethernet is a plus;
• Good verbal and written communication skills, both in Mandarine and English.
• MSEE/CS or BSEE/CS, with 2+ years of related experience.
• No Huawei background on last one year.