(Sr.)Digital Manager
- 40万-80万/年
- 上海
- |
- 5年以上
- |
- 硕士
- |
- 全职
职位诱惑: 年终奖金,福利好,老板nice,年底双薪,股票期权,天天下午茶,年度旅游,技术领先,成长空间大,交通补助,节日礼物,技能培训
发布时间: 2020-06-27发布
职位描述
Responsibilities:
1. Leading digital design team to design and implement high-speed SERDES IPs
2. Leading digital design team to perform algorithm design, RTL coding, analog design modeling, design verification, synthesis, timing closure, emulation and debugging of chips
3. Working with rest of Analog design team for interface definitions.
4. Working with the verification team to enable integration into top level test environments and provide support via functional models
5. Collaborating with the product development team to get the product into high volume applications
6. Mentoring junior engineers
Qualification:
1. MSEE/CS with at least 10+ years of IC digital design experience
2. Hands-on experience with 10Gbps and above SerDes is a plus
3. Very strong skills in Verilog RTL coding and simulation
4. Strong skills in scripting (C, Perl, Skill, MATLAB)
5. Self-motivated, good team work spirit and good communication skills
6. Relevant experiences in high speed SerDes IO design; Ethernet/PCIe/SATA/USB/MIPI is a plus
职位发布者
芯原微
简历处理用时
简历及时处理率
芯原微电子(上海)股份有限公司
领域: 移动手持,消费电子,智能硬件
规模: 500-1000人
主页: http://www.verisilicon.com
工作地址:
上海市浦东新区张江大厦
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