(Sr) Staff Analog engineer

岗位职责：

开发各级CMOS技术中超高速SerDes的高性能模拟/混合信号/逻辑/时钟电路。

工作职责包括：

1) 开发模块的拓扑和规范以及SerDes的顶层;

2) 进行多级设计验证和设计质量/完整性检查;

3) 指导掩模设计人员实现SerDes电路;

4）基于模拟/混合信号设计方法创建设计文档和报告;

5）指导初级工程师，参与芯片评估，确保设计工作符合芯片的设计规范。

岗位要求：

1）电子工程专业硕士或博士

2）至少7年以上SerDes设计的直接经验，包括超宽带放大器、连续时间滤波器、判决反馈均衡器、PLL和低抖动时钟电路、时钟和数据恢复电路、Tx线路驱动、数据并转串和串转并；

3）较强的分析验证能力和芯片评估能力;

4）丰富的超高速模拟电路物理实现知识;

5）具有自适应信号处理或通信系统的知识犹佳。

6）有高速SerDes设计经验如Ethernet/PCIe/SATA/USB/MIPI优先

Responsibilities:

Develop high-performance analog/mixed-signal/logic/clocking circuits for ultra-high speed SerDes in CMOS technologies at all levels.

Job duties include

1）Developing topology and specifications for analog building blocks and top-level for SerDes;

2) Performing multi-level design verifications and design quality/integrity checks;

3) Supervising mask designers on physical implementation of SerDes circuits;

4) Creating design documents and reports based on analog/mixed-signal design methodology;

5) Mentoring junior engineer, and participating in silicon evaluation to ensure design work meet design specifications in silicon.

Qualification:

1) MSEE or PhD required

2) At least 7+ years of direct experiences in SerDes designs including ultra-wideband amplifier, continuous-time filter, decision feedback equalizer, PLL and low jitter clocking circuitry, clock and data recovery circuitry, Tx line driver, data serializer and de-serializer.

3) Strong analytical and verification skills and silicon evaluation skills;

4) Rich knowledge in physical implementation of ultra-high speed analog circuits;

5) Knowledge in adaptive signal processing and/or communication systems is a plus.

6) Relevant experiences in high speed serdes IO design, Ethernet/PCIe/SATA/USB/MIPI is a plus