Staff Digital Engineer

岗位职责：

1. 负责高速SerDes IP的设计与实现

2.负责算法设计，RTL编程，模拟设计建模，验证，综合，时序收敛以及芯片调试

3.和模拟设计团队协同进行接口的定义

4.和验证团队合作以便顶层测试环境的整合

5.和产品团队协作使产品或IP达到量产标准

岗位要求：

1. 电子工程专业或计算机专业硕士或以上

2. 至少5年以上的数字设计经验

3. 有10Gbps或以上SerDes的直接开发经验优先

4. 极强的Verilog RTL编程和仿真能力

5. 较强的脚本编程能力(C, Perl, Skill, MATLAB)

6 有高速SerDes设计经验如Ethernet/PCIe/SATA/USB/MIPI优先

7. 积极主动，有较好的团队协作及沟通技巧

 Responsibilities:

1. Design and implementation of high-speed SERDES IPs

2. Performing algorithm design, RTL coding, analog design modeling, design verification, synthesis, timing closure, emulation and debugging of chips

3. Working with rest of Analog design team for interface definitions.

4. Working with the verification team to enable integration into top level test environments and provide support via functional models

5. Collaborating with the product development team to get the product into high volume applications.

Qualification:

1. MSEE/CS with at least 5+ years of IC digital design experience

2. Hands-on experience with 10Gbps and above SerDes is a plus

3. Very strong skills in Verilog RTL coding and simulation

4. Strong skills in scripting (C, Perl, Skill, MATLAB)

5. Self-motivated, good team work spirit and good communication skills

6. Relevant experiences in high speed serdes IO design, Ethernet/PCIe/SATA/USB/MIPI is a plus