关注微信 意见反馈

扫描关注摩尔人半导体招聘

摩尔人招聘
确定

您已提交成功

查看帮助中心
对职位有兴趣?上传您的简历无需注册,即可直接投递您心仪的职位
泉能研究院

Snr Digital Design Eng/Design Mgr

收藏职位
  • 我要分享
  • 25万-50万/年
  • 济南
  • |
  • 工作经验不限
  • |
  • 本科
  • |
  • 全职

职位诱惑: 福利好,技术领先,成长空间大

发布时间: 2020-06-28发布

职位描述

Our IC Design group is growing and we are looking for a senior digital design engineer/manager to support our Mixed-Signal IC Design team in Jinan. This individual will lead a group that makes significant contributions to all aspects of IC digital design for low-power implantable audio devices. The group has responsibility for concept/specification development, design partitioning and block level design, detailed design, synthesis and simulation, layout floor-planning (cooperation with backend) and transistor/gate level layout, bench verification and testing, test vector development, documentation, release to production and production support. The successful candidate will assign and delegate tasks, clarify priorities and focus the team to drive productivity, and lead the team in identifying and implementing new processes or technologies to increase efficiency and quality.
Your Responsibilities:
-Contribute to the STB/Multimedia IC product digital design efforts
-Able to take designs from architecture concept to micro-architecture. Designs include various digital & mixed-signal interfaces, complex interconnects, block level RTL design/implementation as well.
-Test mode and scan design and implementation
-Participate in chip and block level digital/mixed-signal test bench development with Verilog/System Verilog/UVM
-Optimize designs, trading off performance, power, and area, depending on requirements.
-Implement designs in Verilog/SystemVerilog RTL.
-Work with verification engineer on verification plans, test cases, and analyzing test results
-Debug logic in both simulation and silicon.
-Formulate constraints, perform synthesis, and check static timing.
-Perform formal checks, lint check, and CDC checks.
-Support the backend team for efficient realization of designs.
-Fully document designs and test benches
 
Candidates Requirements:
-An advanced degree in Electrical Engineering (MS / PhD), with relevant work in the field, is highly desirable
-Excellent skills in verbal communication and technical document writing
-Ability to influence and motivate teams
-Strong time management, task management, and interpersonal skills.
-Highly skilled in Verilog, RTL synthesis and verification techniques, and in effectively applying design tools and flows for timing-constrained and power-constrained designs
-Strong grasp of the circuit techniques and trade-offs involved in very low-power digital design, including clock and power gating, multiple VT circuits, sub-threshold and near-threshold digital design, dynamic voltage/frequency scaling, variation-aware/variation-tolerant designs, etc.
-Strong understanding of CMOS processes, device characteristics, and layout techniques and their effects on circuit performance.
-Familiar with ASIC design flow and IC design tools such as VCS, Verilog-XL, Design Compiler, Prime Time, etc..
-Must be proficient in Verilog/VHDL, and digital low power design.
-DFT technique and synthesis, test vector generation and fault coverage simulation.
-Experience on FPGA verification.
-Knowledge at least one of communication interfaces such as UART, I2C, SPI, HDMI, MIPI, PCIe, USB, SATA, Ethernet etc. familiar with more than one is plus.
-Experience of mixed-signal design is preferred.
-Experience in scripting languages such as Python and Perl is a plus.
-Creative, self-motivated, responsible, good team work spirit.

职位发布者

于洪微

HR

4天

简历处理用时

100%

简历及时处理率

您还未登录。已有账号, 点此登录,直接投递

推荐朋友

一键投递
泉能先进集成电路产业研究院

泉能研究院

领域: 智能硬件

规模: 200-500人

主页:

工作地址:

汉峪金谷

查看完整地图