Design Verification Intern_数字验证_暑期实习
- 8万-10万/年
- 上海
- |
- 应届生/在校生
- |
- 硕士
- |
- 实习
职位诱惑: 老板nice,福利好,成长空间大,技术领先
发布时间: 2021-05-07发布
职位描述
Responsibility
1.Co-work with global team to develop key IP for next generation Storage controller
2.Writing Test suits for Storage controllers in UVM environment
3.UVM test bench development
4.Maintain and enhance UVM environment to improve coverage
5.Debugging test benches
6.Perform functional verification of design on block and system level.
Qualifications
1.Candidate MUST be currently pursuing a MS degree in CS/EE or related technical field(s)
2.Familiar with C
3.Good verbal and written English communication skills
4.Familiarity of UVM methodology is a big plus
5.Strong Programming Skills in Scripting/programming language like PERL/Python is a plus.
6.Understanding of Networking Protocols such as IP, TCP etc.
7.Understanding any of this knowledge is a big plus:
- PCIE/NVME Protocol
- NAND Interface Protocol, such as ONFI and Toggle protocol.